1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method of fabricating a fin field-effect transistor, which reduces the number of process steps by forming the fin structure by etching away a predetermined thickness of an element isolation layer.
2. Discussion of the Related Art
A MOS field-effect transistor that is mainly used for a memory semiconductor device, such as a conventional DRAM device, is a substantially planar transistor where a gate insulating layer covers a surface of a silicon substrate and a conductive layer is formed on the gate insulating layer. With increased integration, however, the line width of a gate pattern and the length and width of a channel are reduced, deteriorating transistor operation by, for example, increasing short-channel and narrow-channel effects. Along with the higher integration, a driving current flowing through a substrate channel, underlying the gate electrode in each cell, may flow through a greatly limited depth and width of the channel adjacent to the gate electrode. However, limiting the current levels degrades transistor characteristics.
To overcome short-channel effects and the driving current limitation, the MOS field-effect transistor may be provided with a fin structure to enlarge a contact surface area existing between the substrate and the gate electrode in a shallow junction structure, and thus enable increased levels in the driving current. A contemporary fin field-effect transistor, known as a “finFET,” is shown in FIGS. 1A-1M.
As shown in FIG. 1A, after respectively depositing layers of oxide and nitride on the entire surface of a semiconductor substrate 100 having separately defined active and inactive regions (not shown), each deposited layer is patterned by photolithography and etching processes to form a pad oxide layer 154 and a pad nitride layer 155 in the inactive region. The active region of the semiconductor substrate 100 is thus exposed by a trench 191 formed by etching.
As shown in FIG. 1B, a fin 101 is formed in the trench 191.
As shown in FIG. 1C, the pad oxide layer 154 and the pad nitride layer 155 are removed to form trenches 192 in the inactive regions of the semiconductor substrate 100.
As shown in FIG. 1D, ions are implanted in the fin 101, disposed on the active regions of the semiconductor substrate 100, to form a well region (not shown).
As shown in FIG. 1E, a gate oxide layer 102 is formed by performing a thermal oxidation process or a rapid thermal process with respect to the entire surface of semiconductor substrate 100 on which the fin 101 and well region are formed. Subsequently, a gate electrode polysilicon layer 103 is formed on the entire surface of the semiconductor substrate 100 where the gate oxide layer 102 is formed.
As shown in FIG. 1F, the gate electrode polysilicon layer 103 and gate oxide layer 102 are patterned by photolithography and etching processes to form a gate electrode 149.
As shown in FIG. 1G, a low-concentration ion implantation process for forming a shallow junction region is performed to form a lightly doped junction region 105a (P− or N−) in the fin 101 of the active region.
As shown in FIG. 1H, predetermined deposition and etching processes are formed, to form a spacer 106 on the sidewall of the gate electrode 149.
As shown in FIG. 1I, a high-concentration implantation process is performed to form a heavily doped junction region 105b (P+ or N+) in the fin 101, thereby forming a source/drain region 105 including the lightly doped junction region 105a and the heavily doped junction region 105b. Next, the gate electrode 149 is doped using a low-on concentration ion implantation process.
As shown in FIG. 1J, a photoresist pattern 188 is formed to expose the inactive regions of the semiconductor substrate 100.
As shown in FIG. 1K, using the photoresist pattern 188 as a mask, the inactive regions of the semiconductor substrate 100 are etched to form trenches 193.
As shown in FIG. 1L, the trench 193 is filled with an insulating layer to form an element isolation layer 107.
As shown in FIG. 1M, the photoresist pattern 188 is removed.
The method of fabricating such a fin field-effect transistor has a large number of process steps, which employ numerous masks, which lowers the yield of the product.